1. Field of the Invention
The present invention generally relates to testing electronic circuits and, more particularly, to an automatic test method and system for testing integrated circuit (IC) memory chips, such as dynamic random access memory (DRAM) circuits.
2. Background Description
Usually a bench tester is used to test the access time of a memory chip manually. The procedure is first to pick a reasonable access time to test the memory array at a certain temperature. If the array functions properly, then the array will be tested again with an access time shorter than the originally set time. However, if the array fails, the time is extended. The method is repeated until the array functions properly at the minimum access time, but fails if the time further is shortened by some time interval. The resolution of the time interval is usually determined by the capability of the bench tester. Although the bench tester can be programmed to perform access time analysis, this method is time consuming and of limited accuracy.
Built In Self Test (BIST) can perform on-chip testing of integrated circuits by application of various patterns and voltages utilizing a limited number of timing sets. Variation in the relative timings between address, control and clock signals has been restricted to a few basic patterns. More exhaustive timing tests between input signals can only be done by “schmoo testing” on an external tester, a test sequence which performs testing while varying several parameters. Hence a facet of conventional testing is not possible using existing BIST. Traditional schmoo testing can be performed by sequentially adjusting the timing of a first signal while holding others constant, then incrementing the timing of a second signal and repeating the timing variation of the first signal. Traditional schmoo testing is an important tool to look for unintentional interactions between input timing and stimuli to a macro or logic block. For example, if a memory array is receiving an input signal while its sense amplifiers are setting, wiring resistance can create a ground bounce and cause an input signal to be misread, or delayed. Another classical power rail problem is caused by the simultaneous firing of off-chip drivers (OCDs) while attempting to input a signal for a next operation. A macro may function properly when inputs are received just prior to, and just after, the firing of the OCDs but may have a timing sensitivity and fail a subsequent operation due to a sensitivity to a specific relationship between input stimuli.
U.S. Pat. No. 5,961,653 to Kalter Ct al. discloses a microprocessor based BIST for an embedded memory; however, the complication and density impact of including a microprocessor on an on-chip macro makes this approach inefficient and impractical.